1.6nm, wafer level super packaging, silicon photonic integration... TSMC North America

According to a report from Jiweiwang, TSMC held the 2024 North American Technology Forum in California, USA at the end of April, announcing six major semiconductor technology innovations including its latest semiconductor process technology A16 (1.6nm), next-generation advanced packaging, and 3D chip technology, which attracted industry attention. Under the global trend of developing artificial intelligence (AI), TSMC has become the most important foundry for AI chips such as Nvidia, thanks to its leading chip technology and stable expansion of production capacity.

According to a report from research firm TechInsights, TSMC's total sales in 2023 reached $69.276 billion, becoming the global semiconductor industry champion. Financial service institutions such as JPMorgan Chase and Morgan Stanley have given optimistic predictions for TSMC's future development. In their latest report, Morgan Stanley believes that TSMC's leading position in technological innovation and advanced packaging, as well as its key role in the AI era, is expected to continue to maintain its leading position in the semiconductor industry in the coming years through a series of technological breakthroughs.

The following are the six semiconductor technologies announced by TSMC at the 2024 North American Forum:

A16 1.6nm process technology

The TSMC A16 process node is its first node to integrate nanosheets and back power supply technology "Super Power Rail", making it particularly suitable for high-performance computing (HPC) and artificial intelligence (AI) applications. It is an iteration of TSMC's N2P process. According to TSMC's previously released roadmap, N2 and N2P 2nm nodes are scheduled for mass production in 2025, while A16 is expected to be produced in the second half of 2026.

Compared with 2nm N2P nodes, A16 improves transistor density and energy efficiency, achieving a speed increase of 8-10% at the same Vdd (positive power supply voltage); At the same speed, power consumption can be reduced by 15-20%. This technology can help data center computing chips achieve a chip density of 1.07-1.10 times.

TSMC announced the A14 process node at the North American Summit, which is expected to use second-generation nanosheet transistors and more advanced back power supply networks. Production is expected to begin from 2027 to 2028, and it is not expected to use High NA EUV lithography machines.

According to the roadmap, TSMC's 1nm process A10 is already under planning. Sources revealed in January 2024 that TSMC has planned a more advanced 1nm wafer plant in the Chiayi Science Park and has sent personnel to survey the target site. This location is only a seven minute drive from the Chiayi High Speed Rail Station, connecting TSMC Zhongke and Zhuke factories to the north, and Nanke and Kaohsiung factories to the south, making it convenient for engineers to commute and communicate.

NanoFlex Innovative Nanochip Transistor

TSMC's upcoming N2 process technology will adopt NanoFlex's innovative nanosheet transistor technology, which is another breakthrough in the company's design and technology collaboration optimization. NanoFlex provides design flexibility for N2 process standard units, where short transistor units can achieve smaller area and higher energy efficiency, while high units maximize performance.

Customers can optimize the combination of small and large units within the same design, adjust the design to achieve optimal power consumption, performance, and area balance.

N4C process technology

TSMC announced the launch of N4C technology, which is an iteration of N4P and can reduce chip costs by 8.5%. It is scheduled for mass production in 2025. This technology provides a basic IP and design rules with efficient area utilization, compatible with widely used N4P, reducing chip size and improving yield, providing customers with a cost-effective choice.

CoWoS, SoIC, and System Level Wafers (TSMC SoW)

TSMC stated that CoWoS advanced packaging has become a key technology for AI chips, widely adopted, allowing customers to package more processor cores with HBM high bandwidth storage stacks.

At the same time, Integrated Chip Systems (SoICs) have become a leading solution for 3D chip stacking, and customers are increasingly using CoWoS in conjunction with SoICs and other components to achieve final System Level Package (SiP) integration.

TSMC announced the launch of CoW SoW packaging technology (TSMC SoW), which is an iteration of TSMC's InFO SoW on-chip system integration technology launched in 2020. Through wafer level system integration packaging technology (SoW), large chip arrays can be manufactured on a single 12 inch wafer, providing stronger computing power while reducing space occupation and improving performance by multiple orders of magnitude per watt. Previously, Tesla's Dojo D1 superchip was implemented using TSMC's similar process, utilizing single chip wafers to achieve powerful computing power.

It is reported that the Dojo D1 super chip developed by Tesla adopts TSMC's 7nm process, and is manufactured in combination with the advanced packaging and vertical power supply structure of InFO-SoW, which is used to train the AI model of autonomous vehicle. In terms of parameters, each module contains a total of 25 chips with a size of 5 x 5, and each single chip contains up to 354 cores. Therefore, the on chip SRAM replacement has a total of 11GB and a computing power of 9050TFLOPS.

TSMC stated that its first SoW product - a pure logic wafer based on integrated fanout packaging (InFO) technology - has been put into production. CoW SoW wafers utilizing CoWoS technology are expected to be launched in 2027, which will integrate SoICs, HBMs, and other components to create powerful single crystal wafer level systems with computing power comparable to the entire rack or even the entire server. This type of chip will have a huge area and can integrate four SoIC chips, 12 HBM storage chips, and additional I/O chips, with a power of several kilowatts.

Silicon Photon Integrated COUPE

TSMC is developing Compact Universal Photon Engine (COUPE) technology to support the explosive growth in data transmission brought about by the artificial intelligence boom. COUPE uses SoIC-X chip stacking technology to stack electronic chips on silicon photonic chips and ensure the lowest transmission impedance between the two chips, resulting in higher energy efficiency than traditional stacking methods.

TSMC plans to use COUPE technology for small-sized plug-in devices in 2025, with speeds up to 1.6Tbps, which is exponentially higher than the current state-of-the-art 800G Ethernet. In 2026, TSMC integrated it into CoWoS packaging as a co packaged optical device (CPO), directly introducing optical connections into the packaging, achieving speeds of up to 6.4 Tbps. The third iteration version is expected to be further improved, doubling the speed to 12.8Tbps.

Advanced Packaging of Automotive Chips

After launching the N3AE "Auto Early" process in 2023, TSMC will continue to meet the higher computing power needs of automotive customers and the requirements for vehicle level certification by integrating advanced chips and packaging. TSMC is developing InFO-oS and CoWoS-R solutions for applications such as Advanced Driver Assistance Systems (ADAS), vehicle control, and onboard central computers, with the goal of obtaining AEC-Q100 Level 2 certification by the fourth quarter of 2025.

After the recent TSMC law conference, Daimo predicts that TSMC's Q2 revenue will increase by 5% to 7% month on month, and provides a target stock price forecast of NT $860. Xiaomo predicts that TSMC's gross profit margin will remain in the range of 52% to 54% this year. It is expected that the 3nm production capacity will reach 100000 pieces by the end of this year and will increase to 150000 pieces next year, with a target stock price of NT $900. Xiaomo also predicts that TSMC's market share in AI chips will remain above 90% in the next 3-4 years, and by 2027, the proportion of AI related revenue will rise to 25% of total revenue.

After TSMC's legal conference and multiple technical forums, a steady signal was sent to the market, including financial institutions such as Citibank, Bank of America Securities, and UBS, all providing forecasts for TSMC's annual revenue growth. Driven by the continuous growth of demand in the artificial intelligence market and the release of new production capacity from chip factories in the United States and Japan, it is expected that TSMC will continue to lead the global semiconductor industry in the coming years and maintain its leading position in the AI chip field with its technological strength.